FPGA implementation of short critical path CORDIC-based approximation of the eight-point DCT

This paper presents an efficient approach for multiplierless implementation for eight-point DCT approximation, which based on coordinate rotation digital computer (CORDIC) algorithm. The main design objective is to make critical path of corresponding circuits shorter and reduce the combinational delay of proposed scheme. 1. INTRODUCTION It is well know that the discrete cosine transform (DCT) has been widely used in many areas such as speech and image coding. In particular, the two-dimensional (2-D) DCT has been adopted in some international standards such as MPEG, JPEG and CCITT [1]. A 2-D DCT can be obtained by applying 1-D DCT over the rows followed by a 1-D DCT over the columns of the 8x8 data block [2]. Therefore the efficient implementation of DCT has become the most important issue in developing real-time embedded system. In mobile multimedia devices such as digital cameras, cell phone or pocket PCs hardware complexity as well as power consumption has to be minimized. To do this the great number of fast DCT algorithm were proposed [3], among which Loeffler algorithm [4] gained the lower bound of multiplicative complexity for 8-point DCT. It's required only 11 multiplication and 29 addition. But the common disadvantage of all fast DCT algorithm is that they still need floating point multiplication. These operations are very slow in software implementation and require large area and power in hardware. And therefore can not be used in mobile multimedia devises. So there is still the need to look for new design of DCT algorithm compromises better suited to particular application. Mathematically, fast DCT is composed of additions and multiplications by constants. When implemented in hardware, the multiplication by constants are often implemented by a sequence of additions and shifts which is less expensive in terms of chip area and power consumption [5]. These implementations of transforms are referred to as multiplierless. The binDCT seems to be the most notable result in this field [6]. This transform is based on VLSI-friendly lattice structure and derived from DCT matrix factorization by replacing plane rotations with lifting schemes. Another popular way of multiplierless implementation of DCT is to use the coordinate rotation digital computer (CORDIC) algorithm [7]-[9]. Since the CORDIC algorithm leads to a very regular structure suitable for VLSI implementation.